Work out the pipeline.

One instruction per stage per cycle, in order. Always advance as early as possible. IF → ID → EX → MEM → WB. Repeat IF or ID while held; leave unused cells blank. I1 is filled for you.

Without forwarding: the consumer stays in ID until each producer reaches WB. WB writes in the first half of the cycle; ID reads in the second half of that same cycle.

With forwarding: an ALU result is ready at the end of EX and can feed the next cycle’s EX via MEM-to-EX. A loaded word is ready at the end of MEM and can feed the next cycle’s EX via WB-to-EX. The paths go to EX, not ID. An immediately dependent load-use pair needs one stall.

Stores: the base address can be forwarded to EX. The value to store is read in ID; there is no store-data forwarding here. Show all five stages for sw, including its unused WB. Stores change RAM in MEM and do not change CPU registers.

Instruction and data memories are separate. All addresses are valid and aligned; memory takes one cycle. No branches, cache misses, or other structural hazards. A store commits at the end of MEM, before a later load accesses that address.

Single-issue, in-order, five-stage pipeline with separate instruction and data memories. All source operands are ready; no data stalls, cache misses, or other hazards. Each question has one forward beq $s1, $s2, T. The initial comparison values are given above the grid.

Predict not taken: fetch sequential instructions while the branch is being processed. Compare the operands and resolve the outcome and target at the end of EX.

If taken: cancel the younger instructions occupying ID and IF at that moment. Fetch T in the next cycle. There is no branch delay slot. Any intervening instructions not yet fetched have entirely blank rows.

If not taken: keep executing sequentially. Nothing is flushed, and T is eventually reached in normal program order.

Notation: write the stage occupied at cancellation with ×: ID× or IF×. Leave all later cells blank. A flush is cancellation, not a repeated ID/IF wait. Use this convention for this tool; follow any notation specified on an exam. Show B passing through unused MEM and WB stages; it does not write RAM or a CPU register.

Single-issue, in-order, five-stage pipeline. Each question combines loads, arithmetic, stores and one forward beq. The branch compares the latest values produced by earlier instructions. Initial CPU registers and RAM words are given above; compute final values in decimal.

Without forwarding: wait in ID for every required producer to reach WB. WB writes in the first half; ID reads in the second half of that cycle.

With forwarding: ALU results finish EX; loaded words finish MEM. MEM-to-EX and WB-to-EX can supply ALU inputs, memory base addresses, and the branch comparison. They do not supply ID. An immediately dependent load-use pair, including lw followed by beq, needs one stall. Store data is read in ID and has no bypass here.

Predict not taken: fetch sequentially. Resolve the branch at the end of EX, after any data stalls. If taken, cancel younger instructions in ID/IF, write ID× / IF×, and fetch T next cycle. Leave later cancelled cells and never-fetched rows blank. There is no branch delay slot.

Writes and cancellation: CPU registers change in WB; stores change RAM at the end of MEM. Older instructions in MEM/WB still complete when the branch is taken. The younger cancelled instructions never reach their writes. A flush cannot undo a completed write. Show unused MEM/WB stages for the branch and unused WB for a store.

Separate instruction/data memories, aligned valid addresses, one-cycle memory, no exceptions, cache misses, jumps or loops. Advance as early as possible. I1 is given; each grid has its own saved answers.